How mobility is stressing the chip industry


Qualcomm last week said it was having problems finding enough capacity to manufacture chips designed for mobile phones, something that’s likely to become more common as the physics that govern how we make semiconductors buckles under the demands of our increasingly mobile lives. But this isn’t just about¬†Moore’s Law; this is a story of how the demands for more performance, less power and smaller sizes are all combining to force changes in the chip industry.

Traditionally, chips are made using a process that involves layering materials on top of a silicon wafer. Those materials are built up into the transistors, gates and other formations that allow a computer program to read the ones and zeros of digital language and turn them into a Netflix video on your tablet or a Tweet from your phone. For decades engineers have managed to push more transistors onto a chip by shrinking the amount of space between them, something called moving down the process node.

For example, Qualcomm’s 28 nanometer chips only had 28 nanometer-channels between transistors on the chip. That’s roughly two-thirds a thousand times smaller than the width of a human hair. Historically, shrinking the distance between transistors led to greater performance for a lower power consumption. It’s how Moore’s Law–the axiom coined by Intel’s co-founder Gordon Moore that the number of transistors on a chip will roughly double every 18 months –kept progressing. But the tinier those channels get, the more challenging it is to make them. The cost of the tools used to build smaller chips rises as does the number of defective chips. Many in the industry think we can’t go much further, or if we do so, we’ll add far more costs compared to what we gain.

The industry hit a wall. Now what?

Intel's new 3-D transistors at 22nm.

The chip industry is well aware that it’s about to hit a wall and everyone from Intel to startups have been working on solutions. That’s why last year Intel made a big deal of its 3-D transistors. This is a new way of making transistors that helps address some of the problems that arise from smaller channel widths — a breakthrough that Intel has been working on for 10 years. Other big players in the chip industry, including IBM, ARM and many of the major foundries that make chips for third-parties, have a different design.

Those companies have been working with a different type of 3-D transistor called a FinFET (read all about FinFETs here if you are so inclined) but the process of building up a 3-D multigate transistor is hard, and chips made with this design have more defects. A French wafer provider called Soitec last week said it had designed a special wafer that will help prevent defects in FinFETs. The wafers will cost a bit more, but Steve Longoria, SVP of global strategic business development at Soitec explains that it will save chipmakers money by requiring fewer adaptations in the manufacturing process and will improve the number of usable chips coming off the manufacturing line.

There’s more than 3-D transistors here.

The increasing challenges of making mobile chips is leading to boom times for chip equipment makers like Applied Materials.

But the road to FinFETs is long, so to bridge the gap between the current manufacturing technology Siotec is also offering a wafer that can help make the traditional flat transistors at smaller sizes. ST-Ericsson’s combo Thor modem and application processor is one of the first to use the wafers. A case study from ST Ericsson notes that it has boosted performance by 40 percent while also allowing for 40 percent lower power consumption. This is the sort of technology Qualcomm could take advantage of as well.

Another solution for the challenges associated with moving down the process node are to change the process itself. Startup SuVolta is attempting this with a new way of manufacturing chips as well as IP related to how chips are designed. The SuVolta method works best for systems on a chip, which cram multiple functions and cores onto a single piece of silicon.

So Intel is redesigning the transistor. IBM and multiple foundries are also redesigning the transistor. Siotec is building a new wafer for IBM and its partners. And SuVolta is trying to remake the process used to make chips. There are plenty of other efforts by the chip equipment industry (ask Applied Materials about the big change in the how it plans to stack chips to reduce connecting wires) and by startups that are rethinking the overall design of chips from Lyric Semiconductor to Adapteva.

The chip industry must adapt to deliver the performance we need in lower power envelopes, and the solutions to that problem range from “rip and replace” options like quantum computing to the efforts described above. All of these will help bridge the demand our mobile devices are placing on chips. In the meantime, the increasing complexity is helping chip manufacturing equipment makers like Applied and startups that are seeking a new way.


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