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Today you’ll only find a vacuum tube in a guitar amp or by rooting around in your grandfather’s old Hi-Fi. But vacuum tubes – or at least their underlying principles – may be set to make a resurgence. A team of researchers at the University of Pittsburgh are investigating the possibility of replacing silicon with vacuums as the medium for electron transport in an effort to build faster and more efficient electronic machines.

As Moore’s Law shrinks down the transistor to nanometer size on today’s integrated circuits, the electrons are running out of space to move around, explained principle investigator Hong Koo Kim in a Pitt news release:

The ultimate limit of transistor speed, says Kim, is determined by the “electron transit time,” or the time it takes an electron to travel from one device to the other. Electrons traveling inside a semiconductor device frequently experience collisions or scattering in the solid-state medium. Kim likens this to driving a vehicle on a bumpy road—cars cannot speed up very much. Likewise, the electron energy needed to produce faster electronics is hindered.

The best way to avoid that kind of scattering is to use no medium at all, either a “vacuum or the air in a nanometer scale space.” Kim said. “Think of it as an airplane in the sky creating an unobstructed journey to its destination,” he said.

Kim isn’t advocating a return to the old red-hot vacuum tube, rather he and his team are building on today’s silicon foundations. They’re developing a method in which electrons can be extracted from semiconductors into the air and then directed via vacuum channels over the surface of the circuit.

If the Pitt researchers can develop a commercially viable vacuum channel technology, it could mean another revolution in microelectronics, creating a new class of high-speed and low-power transistors. That would allow chipmakers to keep riding Moore’s Law and device makers to build more powerful computers, smartphones and tablets that drain less energy.

Kim’s team published their conclusions this month in the journal Nature Nanotechnology. But for a more concise – and entertaining – explanation of their efforts check out the Nation Science Foundation’s podcast on the top: Vac to the Future.

Photo courtesy of Shutterstock user SPbPhoto

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Traditionally, chips are made using a process that involves layering materials on top of a silicon wafer. Those materials are built up into the transistors, gates and other formations that allow a computer program to read the ones and zeros of digital language and turn them into a Netflix video on your tablet or a Tweet from your phone. For decades engineers have managed to push more transistors onto a chip by shrinking the amount of space between them, something called moving down the process node.

For example, Qualcomm’s 28 nanometer chips only had 28 nanometer-channels between transistors on the chip. That’s roughly two-thirds a thousand times smaller than the width of a human hair. Historically, shrinking the distance between transistors led to greater performance for a lower power consumption. It’s how Moore’s Law–the axiom coined by Intel’s co-founder Gordon Moore that the number of transistors on a chip will roughly double every 18 months –kept progressing. But the tinier those channels get, the more challenging it is to make them. The cost of the tools used to build smaller chips rises as does the number of defective chips. Many in the industry think we can’t go much further, or if we do so, we’ll add far more costs compared to what we gain.

The industry hit a wall. Now what?

Intel's new 3-D transistors at 22nm.

The chip industry is well aware that it’s about to hit a wall and everyone from Intel to startups have been working on solutions. That’s why last year Intel made a big deal of its 3-D transistors. This is a new way of making transistors that helps address some of the problems that arise from smaller channel widths — a breakthrough that Intel has been working on for 10 years. Other big players in the chip industry, including IBM, ARM and many of the major foundries that make chips for third-parties, have a different design.

Those companies have been working with a different type of 3-D transistor called a FinFET (read all about FinFETs here if you are so inclined) but the process of building up a 3-D multigate transistor is hard, and chips made with this design have more defects. A French wafer provider called Soitec last week said it had designed a special wafer that will help prevent defects in FinFETs. The wafers will cost a bit more, but Steve Longoria, SVP of global strategic business development at Soitec explains that it will save chipmakers money by requiring fewer adaptations in the manufacturing process and will improve the number of usable chips coming off the manufacturing line.

There’s more than 3-D transistors here.

The increasing challenges of making mobile chips is leading to boom times for chip equipment makers like Applied Materials.

But the road to FinFETs is long, so to bridge the gap between the current manufacturing technology Siotec is also offering a wafer that can help make the traditional flat transistors at smaller sizes. ST-Ericsson’s combo Thor modem and application processor is one of the first to use the wafers. A case study from ST Ericsson notes that it has boosted performance by 40 percent while also allowing for 40 percent lower power consumption. This is the sort of technology Qualcomm could take advantage of as well.

Another solution for the challenges associated with moving down the process node are to change the process itself. Startup SuVolta is attempting this with a new way of manufacturing chips as well as IP related to how chips are designed. The SuVolta method works best for systems on a chip, which cram multiple functions and cores onto a single piece of silicon.

So Intel is redesigning the transistor. IBM and multiple foundries are also redesigning the transistor. Siotec is building a new wafer for IBM and its partners. And SuVolta is trying to remake the process used to make chips. There are plenty of other efforts by the chip equipment industry (ask Applied Materials about the big change in the how it plans to stack chips to reduce connecting wires) and by startups that are rethinking the overall design of chips from Lyric Semiconductor to Adapteva.

The chip industry must adapt to deliver the performance we need in lower power envelopes, and the solutions to that problem range from “rip and replace” options like quantum computing to the efforts described above. All of these will help bridge the demand our mobile devices are placing on chips. In the meantime, the increasing complexity is helping chip manufacturing equipment makers like Applied and startups that are seeking a new way.

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Chips made using its technique have recently run at full speed but consumed half the power of their counterparts that use traditional transistors. This isn’t just a concern of a crazy startup; Intel recently unveiled a new process technology using 3-D transistors that is designed to save on power by helping chips continue to get smaller.

However, SuVolta’s process is pretty sweet because it uses the existing manufacturing tools already in place at the multi-billion semiconductor manufacturing plants, and because it should continue to work as designers shrink their chips. SuVolta also licenses some IP that gives designers a way to tweak their circuits to optimize the efficacy of the power-saving transistors.

It’s also designed to work best for systems on a chip, which are clusters of different processors integrated on one piece of silicon. In PCs and servers, a single or multi-core CPU was the ideal design choice, but for mobile devices and consumer products, integrating a bunch of different types of cores on a single chip has won out because it saves on space and power. This is why I listed SuVolta one of the three startups that showcase the future of chips.

And saving on space and power is the name of the game as devices go mobile and energy becomes a huge issue, either because of battery life or because power generation has become such a limiting factor in the data center. In fact, many of the chip companies that have managed to raise money in the last two or three years are working to reduce power either through some new process or through using new architectures to perform work more efficiently. Companies such as Adapteva, which is using a different architecture to deliver performance with less power in supercomputers and phones; Calxeda, which is trying to use ARM-based chips for low-power servers; and Lyric Semiconductor, which is focused on a new type of computing, all have raised money in the last few years.

But to show how rare such capital-intensive chip deals are, SuVolta pulled together this infographic to drive it home. As a chip reporter who once covered the bubble years when chip startups were a dime a dozen, I live this shrinkage, because there are fewer pitches and fun stories to write, but this makes it easy for everyone to see what’s going on.

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Racetrack memory: IBM’s racetrack memory offers the ability to store massive quantities of information like hard drives do but has no moving parts like solid state drives do, so it’s faster. It’s called a racetrack because it pushes electrons around a wire kind of like a car goes around a racetrack. After years of research, IBM said Monday it can make such devices.

This still isn’t mass production, and the big challenge here is making it power-efficient (driving those electronics through the racetrack requires a big current), but it could provide a means to a new type of faster computing. As IBM said in its release, “This breakthrough could lead to a new type of data-centric computing that allows massive amounts of stored information to be accessed in less than a billionth of a second.”

Here is a video I did back in 2010 at IBM’s Spintronics lab that explains racetrack memory and how it relates to storing more data that can be read faster.

Graphene: IBM also made two materials breakthroughs, beginning with a way to build chips using a carbon-based material called graphene. Graphene could offer better wireless chips because it could allow chips to deliver data over higher frequency bands, and also could lead to long-lasting batteries and breakthroughs in clean energy. Taking advantage of higher frequencies means we could use more of the airwaves and help assuage our growing demand for wireless broadband.

The challenge with graphene is figuring out how to use it in today’s chipmaking fabrication plants, to avoid the multi-billion-dollar costs associated with building such a plant solely to produce graphene chips. IBM said today that it had solved this problem– building a graphene-based chip that is compatible with conventional (CMOS) chipmaking technologies.

Carbon nanotubes: The carbon nanotube announcement is a bit more out there, with researchers demonstrating the first transistor with channel lengths that are smaller than 10 nanometers built using carbon nanotubes. The channel length refers to how deep the lines on a chip are etched, and the goal is to make those smaller and smaller in order to fit more chips on a wafer and continue pushing Moore’s Law forward.

But as transistor channel lengths shrink, conventional chipmaking technologies are running into a variety of problems, which is why Intel made such a big deal of its 3-D transistors earlier this year. However, it’s not clear if that advance will continue below 11 nanometers. Of course, as researchers seek ever smaller chips, some are abandoning the idea of the transistor completely with technologies such as DNA computing, Quantum computing and even brain-like computers. For the time being, IBM’s carbon nanotubes are still in that commercialization phase along with these other efforts, so don’t break out the bubbly just yet.

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Far right is the new chip on a board.

A soup-to-nuts approach.

That’s the hope anyway, although IBM isn’t alone in its efforts to rethink the way computers are built. HP has a different initiative aimed at creating chips that can process more data more power efficiently by changing the basic building blocks inside the chip. Other companies and labs are eyeing quantum computing and other far-fetched ideas (GigaOM Pro sub req’d). But IBM being IBM has both the money and the vision to bring an entirely new way of computing forward — in fact it has been laying the groundwork for years.

Remember these commercials where IBM can tell someone in corporate HQ where a single item is on a truck out in the middle of nowhere? These commercials are from 2005, and ever since IBM has been building the infrastructure in terms of its services business, its software and even with hardware designed to process massive amounts of information on the fly. Watson, the Jeopardy-playing computer is a wonderful example of how far IBM was willing to take the hardware. But most people there knew the hardware was never going to get to the place where IBM’s customers could not only locate one of thousands of trucks to tell it that it was lost, but to the point where the customers could measure everything about that truck from its speed to the temperature inside the containers it held and than send alerts based on those variables. And the system could do all this while consuming a kilowatt of power and in a box the size of a shoebox.

Using brainpower to solve architecture problems.

A cognitive computer playing Pong.

Today’s chips run into a problem called the Von Neumann bottleneck, which is when the chip cannot feed the data in the memory to the processing core fast enough. Without the data the chip idles and the incredible clock speeds we’ve built into chips are somewhat wasted. The neurosynaptic chip throws that model away and relies instead on tracking relationships between events and determining if those events lead to action. When the “neurons” on the chip fire, it sets of a binary response that the processors in each neuron evaluate. When enough feedback comes from that neuron or neurons nearby the system then “understands” where that information fits in, and the chip can make a decision to react to that series of stimuli. Fundamentally, this chip learns.

Dharmendra Modha, project leader for IBM Research, explains that most programmers write code that delivers a lot of instructions to the processor followed by a few if/then statements that describe actions. The neurosynaptic chip doesn’t need those if/then statements because it’s making those correlations itself based on how often it’s “neurons” fire off ones or zeros. This means that IBM’s new chip requires a completely different type of programming (and that it’s suited to completely different types of jobs than today’s chips).

Cognitive Computing and why it matters.

IBM calls this new computing cognitive computing and the goal is to take today’s itty-bitty neurosynaptic chip, which can today play Pong or steer a toy race car around a track, and create a machine that can combine the equivalent of 10 billion neurons all in the size of a shoebox that consumes less than a kilowatt of power. Such a machine would be cable of doing much more, although perhaps one would need multiple machines to create Modha’s vision of a sensor network in every ocean tracking ambient temperature, water turbidity and other metrics to warn folks of an upcoming storm or tsunami. Today’s chip in addition to playing Pong, might be useful if attached to a door where it could “learn when to open the door to let the cat out,” suggested Modha.

“The goal is not to replace today’s computers. It’s to really take the road less traveled and build new generation of computers with a totally new approach to problems in business and science and government,” Modha says. “If today’s computers are left brained, rational and sequential then cognitive computing is intuitive and right-brained and slow, but the two together can become the future of our civilization’s computing stack.”

That’s a big vision, but IBM’s a big company and one that has managed to influence the course of computing before. For more on the science check out the video I shot last year with Modha in his newly built lab at IBM’s Alamaden Research Lab in California.

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I had the privilege of keynoting the inaugural IEEE Technology Time Machine Symposium last week in Hong Kong, where I listened to the world’s leading academics, engineers, executives, and government officials project what the world will look like in 2020. Their predictions were based on revolutionary technologies for processing, sensors, and displays becoming integrated into global systems that can do everything from enhance the human experience to improve environmental sustainability.

Predicting the future is a challenge, since its course depends on rapidly changing technologies integrated into large-scale systems whose acceptance will depend on human behavior, global demographics, and macroeconomic and political dynamics. Nevertheless, the IEEE Technology Time Machine Symposium helped provide a glimpse into the possible. As Rico Malvar, chief scientist of Microsoft Research pointed out, today’s innovative new products such as Microsoft’s Kinect require interdisciplinary collaboration. In the case of the Kinect, that collaboration spanned computer vision, machine learning, human computer interaction, speech recognition, and more.

The components

Intel's new 3-D transistors at 22nm.

I began my keynote by reviewing a number of disruptive technologies that are surprisingly far along. These include Intel’s “Ivy Bridge” Tri-Gate 3-D transistors, which are built vertically like a skyscraper instead of horizontally like a mall, and are being readied for production in 2012; quantum computers, which are no longer just a theoretical concept, but are being shipped commercially; and the long-theorized fourth circuit element, the memristor, now prototyped by HP, may find use in replicating the function of the human brain (sub. req’d). Plus chips aren’t just for processing or memory: Wouter Leibbrandt of the Advanced Systems Lab at NXP Semiconductors, stated that NXP’s new sensor chip has the power of the original Pentium chip but fits on the head of a pin: beginning to make the possibility of “smart dust” sensors a reality. All of the technology means smarter processing power will be faster, smaller and cheaper.

The devices

Displays are getting thinner, lighter, higher-resolution and more power-efficient, using various approaches such as OLED and e-Ink. Experts such as Prof. Hoi-Sing Kwok of Hong Kong’s University of Science & Technology (HKUST) were confident that transparent, flexible, color touchscreen displays are, well, on a roll and just around the bend with existing prototypes continuing to improve.

If you like HD, just wait. While today’s 1080p displays have a resolution of 2 Megapixels (1K x 2K), 35 Megapixel displays have been already been fabricated, 100-Megapixel tiled displays are commercially available, and 287-Megapixel tiled video walls have been constructed.How much is enough? Kwok has calculated that a medium-sized room fully enabled with video walls at the resolution of the human eye would need 3 Gigapixels, 1500 times today’s HD. Such a room might be useful for viewing HKUST’s record-breaking photograph, which is over 150 Gigapixels.

One surprising challenge in building large displays is that distributing TVs at an economically attractive scale requires using today’s transportation infrastructure, limiting the size of the glass to one car lane wide and short enough to fit under an overpass. However, wall-sized flexible displays could be rolled up, shipped, and carried through the front door.

While today’s 3-D approaches have an uncertain future, Kwok believes the most promising 3-D display technology is electro-holographic (picture Princess Leia’s “Help me, Obi-wan.”) A challenge for large, high-resolution displays and electro-holographic displays is not just the display itself, but the processing power required to drive it. Moore’s Law and the technologies I reviewed above should help. Large images may not require large devices; Kwok expects every cell phone to have a pico-projector—a laser projector that can project onto a surface larger than the device—incorporated, the same way that every cell phone now has a camera.

It’s not news that touch screens are becoming popular, but the next enhancement will be “hover” touchscreens, enabling gestural interfaces without touch, where each pixel is also a sensor. Such technology was shown off last year and would require adoption by device makers as well as developers.

At the other end of the spectrum are very small displays. The next generation mobile devices may not be handheld, but perch on your nose, or float on your retina. Masahiro Fujita, president of Sony Systems Technologies Laboratories, outlined a concept for eyeglasses with transparent lenses that double as augmented reality displays, wirelessly linked to your social network and real-time information, providing you live information as you visually scan. It could offer details such as, “That’s the restaurant where Bobby had that great salad, and, it’s got a table free in 10 minutes!”, or, as Jian Ma, chief scientist of the Wuxi Sensing Institute wryly observed, could alert a traveler that “your luggage is no longer with you.”

The next step is the wireless contact lens display, which is already under development. Ultimately, though, devices won’t be something we wear, but something we implant. Brain-computer interfaces that let us control devices using our mind (PDF), or directly stimulate the cortex for artificial vision have been built.

Sound is also important. Fujita of Sony demonstrated a 7.1 channel sound system with “high” front speakers and a “high” mix, enabling sound sources to traverse not only left to right, but also top to bottom. If that’s not enough, NHK has been experimenting with 22.2 channel sound that delivers more surround sound with 24 speakers. Next-generation gaming and entertainment will leverage all of these approaches: Fujita played a cinema-quality video of racing cars, challenging the audience to determine which components were real and which were computer-generated (answer: everything was CGI), pointing out that the vehicle dynamics (bouncing, traction) could be generated interactively in real time.

So what does all this mean for the networks and the backend systems? Please read Part 2 on Sunday for the details.

Joe Weinman leads Communications, Media, and Entertainment Industry Solutions for Hewlett-Packard. The views expressed herein are his own.

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Lowering the power consumption of chips has become a rallying call for the chip industry. SuVolta is also doing its bit so that battery-powered mobile devices will last longer and server makers can deliver computing without requiring data centers to have their own power plants — a theoretical future that could grind the current wave of web services and cloud computing innovations to a halt. The startup has the backing of several A-listers in the chip world, such as Andy Bechtolsheim, Wilfred Corrigan (the founder of LSI Logic) and Bill Joy (Sun Microsystems co-founder, now with Kleiner Perkins, Caufield & Byers).

SuVolta was founded in  2006, and it raised $36.5 million in three rounds through 2009 from investors, including angels such as Bechtolsheim and Corrigan and venture firms including Kleiner Perkins and others. But it ran into stormy weather  — a situation not uncommon in the chip industry. So it was recapitalized in 2010 with $22 million from NEA, August Capital and Kleiner Perkins after getting new management.

The new executive team is headed by McWilliams, who has worked at Tessera and Flextronics, and Scott Thompson as the CTO. Thompson was an Intel fellow who worked on many types of process technologies, both to lower the power consumption in chips but also to continue shrinking them and cramming more transistors on them. We recently covered Intel’s new type of 3-D transistor it announced with much fanfare in May.

SuVolta’s tech, however, is less revolutionary than changing the design of the transistor. At an early point in the manufacturing process (it won’t disclose the point), the SuVolta technology calls for a slightly different combination of ingredients to be layered on the chip. Semiconductors are manufactured in a manner similar to layer cakes, with each layer of circuitry deposited on the chip and the unnecessary bits etched away according to whatever pattern the manufacturer is supposed to follow. Thompson says that SuVolta’s process, which will be available next year, doesn’t change the overall chip-making process. It doesn’t change the silicon used to make the chip, and it can be easily implemented in fabrication plants that will license SuVolta’s technology.

That’s not all. The company says that in addition to the modifications to the manufacturing process, it has developed new circuit design elements that will boost the efficiency even more. McWilliams plans on selling licenses much like ARM does to chip makers, although this tweak doesn’t change the instruction set (so an x86-based chip from Intel or AMD will still operate as an x86 chip, while a chip based on the ARM architecture is still able to run software for those chips).

Unlike building a new chip and finding buyers for it, SuVolta has to convince chip foundries such as Taiwan Semiconductor Manufacturing Company; chip makers such as Qualcomm and Broadcom; and even chip equipment makers such as Applied Materials to embrace its new technology. Fujitsu Semiconductor has signed on as the first licensee. Let’s hope there will be others — for the sake of our power-hungry smartphones.

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The shift is a move from creating scads of information in a format that can be stored cheaply, to being able to process and analyze that information more cheaply as well (all the while adding new layers of data thanks to a proliferation of devices and networks). The challenge is that under the current computing paradigm, adding more processing is problematic both because it’s becoming more difficult to cram more transistors onto a chip, and those chips and their surrounding servers are sucking up an increasing amount of power.

With Power Consumption, The Question is, “How Low Can You Go?”

“Data is expanding faster than Moore’s Law and that’s a compelling problem that we’re trying to solve,” Ranganathan said. It’s apparently a problem that Intel’s Kirk Skaugen, vice president and general manager of the chipmaker’s Data Center Group, is thinking about too. Skaugen said at a speech last week at Interop that there were 150 exabytes of traffic on the Internet in 2009, and 245 exabytes in 2010, and the Internet could hit 1,000 exabytes of traffic by 2015 thanks to more than one billion people joining the web.

Want to hook one of these to your data center?

That’s a lot of bandwidth. But it’s also a lot of data and a lot of compute demand. Listening to Skaugen’s speech it appears that Intel’s primary function will be to convince the people who build the machines that process those exabytes of data, that their machines should run newer and more energy-efficient Intel processors. But is Intel’s architecture — and an upsell to its trigate 3-D transistors — the right chip for computing and big data’s future?

As I noted before, Intel’s much vaunted 3-D transistor advancement is cool, but only gets us so far in cramming more transistors on a chip and reducing the energy level needed. For example, a 22 nanometer chip using the 3-D transistor structure consumes about 50 percent less energy than the current generation Intel chip, but less than an Intel chip using the older architecture would at 22 nanometers (squeezing in more transistors also helps reduce the power consumption). And when we’re talking about adding a billion more people to the web, or transitioning to the next generation of supercomputing, a 50 percent reduction in energy consumption on the CPU is only going to get us so far.

The original, "flat" transistor at 32nm.

For example, scientists at the Department of Defense estimate (GigaOM Pro sub. req’d) that getting to the next generation of supercomputer at the current architectures would require possibly two power plants to serve every exascale computer — reducing that to one is great, but it’s not good enough. This is why the folks at ARM think they have an opportunity and why the use of GPUs in high performance computing is on the rise.

A New Architecture for a New Era

But there is more to this trend than merely eking more performance for less power — there is also a more subtle shift to matching your processors to your workloads in an acknowledgment that generic CPUs running x86 processors might not be the best solution for all workloads, especially in a cloud world. For example, startups are already trying to build optimized gear for companies such as Facebook or Google that can then run their own software on top of these optimized platforms.

Facebook's vanity-free server.

Don’t believe this is coming? Take a look at Facebook’s Open Compute efforts. This kept the same x86 processors made by Intel and AMD, but it was willing to question everything about the architecture of the servers and data centers those chips were house in. And that willingness to question everything is occurring at firms all over the world that are dealing with massive compute needs– a trend Intel can’t help but find worrying and folks such as Ranganathan at HP see as their big chance.

“Historically there is evidence that each killer app has an influence on the architectures that are preceded by the special purpose alternatives,” Ranganathan said. “So asking what instruction set for the processor, or if you want powerful or wimpy processors or special purpose processors are all legitimate architectural questions that we need to answer.”

HP’s answer is its concept of nanostores, chips that tie the memory and the processor together using a completely new kind of circuit called a memristor. The basic premise for HP is that 80 percent of the energy inside a data center is tied to moving data from memory to the processor and then back again. We’re already seeing the trend of moving memory closer to the processor (that’s what the addition of Flash inside the data center is about) to speed up computing.

But instead of next-door neighbors inside a box, HP essentially wants processing and memory married and in the same bed. HP won’t give a timeline on when this vision will become reality, but it has a manufacturing partnership with Hyinx it announced in 2010 to build such chips.

So Where’s Intel in This Architecture?

So when Skaugen gets up at Interop to push Intel’s 3-D transistors and the incredible inflows of data coming online he’s also making a pitch for Intel’s relevancy because big data processing is one of the areas where a general purpose CPU makes a lot of sense. So while folks may adopt GPUs for better supercomputing or data visualizations, or ARM may keep its upward momentum into more and more mobile computers or win some server designs in webscale businesses that can see a use case, just crunching those numbers associated with big data could become Intel’s game to lose.

There are plenty of folks hoping Intel will lose it (or at least that they will stand to gain) — not just Ranganathan at HP, but also the guys building 100-core chips at Tilera, or those hoping that the mathematical affinities inside digital signal processors might make them a good choice for data. It’s a topic I can’t wait to explore with Ranganathan, folks from Intel, Tilera and others at our Structure 2011 event on June 22 and 23. Because just like the steam engines and trains of the Industrial Age had to give way to the tools of the Information Age, the PCs and current servers used today will become a footnote as we pass into the Insight Age.

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